Bit map control of erase block defect list in a memory
US7675776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.