Patent · US Active

System and method of processing data using scalar/vector instructions

US7676647B2 · kind B2 · utility

28Cited by

13References

32Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Lucian Codrescu · Austin, US
Erich James Plondke · Austin, US
Taylor Simpson · Austin, US

Key dates

Filing date	Aug 18, 2006
Grant date	Mar 9, 2010
Priority date	—
Expiry date	Apr 28, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3885
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.