Erich James Plondke
65Patents
8h-index
49Co-inventors
74Inventor score
Filing activity: Mar 21, 2005 → Aug 31, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7676647B2 | System and method of processing data using scalar/vector instructions | Physics | 28 | Active |
| US8243100B2 | System and method to perform fast rotation operations | Physics | 14 | Active |
| US8140823B2 | Multithreaded processor with lock indicator | Emerging Cross-Sectional Technologies | 13 | Active |
| US8756601B2 | Memory coherency acceleration via virtual machine migration | Physics | 12 | Active |
| US7398371B2 | Shared translation look-aside buffer and method | Emerging Cross-Sectional Technologies | 11 | Expired |
| US8190854B2 | System and method of processing data using scalar/vector instructions | Physics | 9 | Active |
| US8250332B2 | Partitioned replacement for cache memory | Physics | 9 | Active |
| US9147123B2 | System and method to perform feature detection and to determine a feature score | Physics | 8 | Active |
| US8656145B2 | Methods and systems for allocating interrupts in a multithreaded processor | Physics | 8 | Active |
| US7917907B2 | Method and system for variable thread allocation and switching in a multithreaded processor | Physics | 8 | Active |
| US9396012B2 | Systems and methods of using a hypervisor with guest operating systems and virtual processors | Physics | 7 | Active |
| US8417922B2 | Method and system to combine multiple register units within a microprocessor | Physics | 4 | Active |
| US8972642B2 | Low latency two-level interrupt controller interface to multi-threaded processor | Physics | 4 | Active |
| US7590824B2 | Mixed superscalar and VLIW instruction issuing and processing method and system | Physics | 4 | Expired |
| US9606818B2 | Systems and methods of executing multiple hypervisors using multiple sets of processors | Physics | 4 | Active |
| US9823928B2 | FIFO load instruction | Physics | 4 | Active |
| US7523295B2 | Processor and method of grouping and executing dependent instructions in a packet | Physics | 4 | Expired |
| US9207943B2 | Real time multithreaded scheduler and scheduling method | Physics | 4 | Active |
| US8479207B2 | Priority inheritance in multithreaded systems | Physics | 4 | Active |
| US7383420B2 | Processor and method of indirect register read and write operations | Physics | 3 | Expired |
| US9390264B2 | Hardware-based stack control information protection | Physics | 3 | Active |
| US8631056B2 | Processor and method of determining a normalization count | Physics | 3 | Active |
| US8281111B2 | System and method to execute a linear feedback-shift instruction | Physics | 3 | Active |
| US10114756B2 | Externally programmable memory management unit | Physics | 3 | Active |
| US8990543B2 | System and method for generating and using predicates within a single instruction packet | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.