Delay locked loop circuit and synchronous memory device including the same
US7676686B2 · kind B2 · utility
8Cited by
11References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The present invention can prevent a phase update operation from being interrupted when the DLL circuit enters a power-down mode. For the above purpose, an off operation of a clock buffer is delayed until a clock signal notifying a final period of the phase update is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.