Logic block timing estimation using conesize
US7676779B2 · kind B2 · utility
1Cited by
10References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.