Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method

US7678679B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Dirk Manger · Dresden, DE
• Jyoti Gupta · Singapore, SG
• Christoph Ludwig · Radeberg, DE
• Hans Lindemann · Dresden, DE

Key dates

• Filing date: May 1, 2006
• Grant date: Mar 16, 2010
• Expiry date: Dec 4, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/015
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.