Fabrication method for a damascene bit line contact plug
US7678692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jan 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.