Transistor performance enhancement using engineered strains
US7679145B2 · kind B2 · utility
3Cited by
23References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Aug 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.