Programming and/or erasing a memory device in response to its program and/or erase history
US7679961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.