Resistive memory including selective refresh operation
US7679980B2 · kind B2 · utility
15Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Apr 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.