Multithreading instruction scheduler employing thread group priorities
US7681014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction dispatching apparatus in a multi threading microprocessor that concurrently executes N threads each in one of G groups each having one of P priorities. G round-robin vectors each have N bits corresponding to the threads, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit vector with a single bit true of the last thread selected for dispatching in the group. Each of N G-input muxes receive a corresponding one of the N bits of each of the round-robin vectors and selects for output one of the inputs specified by the corresponding thread's group. Selection logic selects for dispatching one of the N instructions corresponding to the thread whose dispatch value is greater than or equal to any of the N threads left thereof. Each dispatch value comprises a least-significant bit of the corresponding mux output, a most-significant dispatchable instruction bit, and middle thread group priority bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.