Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test
US7681099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Feb 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31727
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.