Air gap for interconnect application
US7682963B2 · kind B2 · utility
7Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Sep 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.