Method to improve profile control and N/P loading in dual doped gate applications

US7682980B2 · kind B2 · utility

Assignee

• Lam Research Corporation · US

Inventors

• Helene Del Puppo · Fremont, US
• Frank Y. Lin · Fremont, US
• Chris Lee · Oakland, US
• Vahid Vahedi · Oakland, US
• Thomas A. Kamp · San Jose, US
• Alan J. Miller · Fremont, US
• Saurabh Ullal · Berkeley, US
• Harmeet Singh · Simsbury, US

Key dates

• Filing date: Jan 25, 2007
• Grant date: Mar 23, 2010
• Expiry date: Jun 22, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32137
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.