Thermal treatment of nitrided oxide to improve negative bias thermal instability
US7682988B2 · kind B2 · utility
1Cited by
5References
21Claims
0Family size
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Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.