Semiconductor package having dimpled plate interconnections
US7683464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.