Resistive memory architectures with multiple memory cells per access device
US7684227B2 · kind B2 · utility
14Cited by
6References
57Claims
0Family size
Assignee
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Key dates
| Filing date | May 31, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Nov 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.