Area efficient and fast static random access memory circuit and method
US7684257B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Dec 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an accumulation memory circuit for providing a fast read, modify, and write operation in a single clock cycle time. The memory circuit is configured to read data stored in the memory device at an address. The memory circuit includes a reconfigurable adder unit generating read, accumulate and write output in a single clock cycle. The memory circuit is further configured to minimize data overflow. A high speed accumulation method comprises resetting a memory circuit; reading from an address of the memory circuit; performing internal addition within the memory circuit and rewriting into the address of the memory circuit in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.