Stacked integrated circuit package system and method of manufacture therefor
US7687315B2 · kind B2 · utility
8Cited by
209References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Mar 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.