Methods for fabricating FinFET structures having different channel lengths
US7687339B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2009 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Feb 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0245
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating a FinFET structure are provided. One method comprises forming a hard mask layer on a gate-forming material layer having a first portion and a second portion. A plurality of mandrels are fabricated on the hard mask layer and overlying the first portion and the second portion of the gate-forming material layer. A sidewall spacer material layer is deposited overlying the plurality of mandrels. The sidewall spacer material layer overlying the first portion of the gate-forming material layer is partially etched. Sidewall spacers are fabricated from the sidewall spacer material layer, the sidewall spacers being adjacent sidewalls of the plurality of mandrels. The plurality of mandrels are removed, the hard mask layer is etched using the sidewall spacers as an etch mask, and the gate-forming material layer is etched using the etched hard mask layer as an etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.