Formation of shallow siGe conduction channel
US7687356B2 · kind B2 · utility
10Cited by
26References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/385
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.