Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall
US7687381B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 19, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Mar 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.