Inventor · Singapore, SG

Johnny Widodo

21Patents

4h-index

58Co-inventors

58Inventor score

Filing activity: Feb 22, 2006 → Aug 2, 2010

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7524755B2	Entire encapsulation of Cu interconnects using self-aligned CuSiN film	Electricity	26	Expired
US7566656B2	Method and apparatus for providing void structures	Electricity	12	Active
US7847402B2	BEOL interconnect structures with improved resistance to stress	Electricity	4	Active
US7838390B2	Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein	Electricity	4	Active
US8716081B2	Capacitor top plate over source/drain to form a 1T memory device	Electricity	4	Active
US8178417B2	Method of forming shallow trench isolation structures for integrated circuits	Electricity	4	Active
US8274115B2	Hybrid orientation substrate with stress layer	Electricity	3	Active
US7687381B2	Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall	Electricity	3	Active
US8053327B2	Method of manufacture of an integrated circuit system with self-aligned isolation structures	Electricity	2	Active
US7923365B2	Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon	Electricity	2	Active
US7541288B2	Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques	Electricity	1	Active
US7622403B2	Semiconductor processing system with ultra low-K dielectric	Electricity	1	Active
US7459388B2	Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses	Electricity	1	Active
US7906426B2	Method of controlled low-k via etch for Cu interconnections	Electricity	0	Active
US7829422B2	Integrated circuit having ultralow-K dielectric layer	Electricity	0	Active
US7767577B2	Nested and isolated transistors with reduced impedance difference	Electricity	0	Active
US7999300B2	Memory cell structure and method for fabrication thereof	Emerging Cross-Sectional Technologies	0	Active
US7737029B2	Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby	Electricity	0	Active
US7932178B2	Integrated circuit having a plurality of MOSFET devices	Electricity	0	Active
US8143651B2	Nested and isolated transistors with reduced impedance difference	Electricity	0	Active
US7795680B2	Integrated circuit system employing selective epitaxial growth technology	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.