Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system
US7689809B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. A system includes a master processor having a first state, a slave processor having a second state, and a buffer memory. The system is operable to switch from a parallel mode to a serial mode responsive to an interrupt or exception and save the states to the buffer memory. Responsive to t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.