Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
US7689813B2 · kind B2 · utility
5Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2005 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.