Multicore chip test
US7689884B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Apr 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.