Patent · US Active

Programmable via modeling

US7689960B2 · kind B2 · utility

5Cited by

33References

8Claims

0Family size

Assignee

eASIC CORPORATION · US

Inventors

Jonathan Park · San Jose, US
Yit Ping Kok · Permatang Pauh, MY
Soon Chieh Lim · Merang, MY
Yin Hao Liew · Bukit Mertajam, MY
Wai Leng Chek · Air Itam, MY

Key dates

Filing date	Jan 25, 2006
Grant date	Mar 30, 2010
Priority date	—
Expiry date	Jul 22, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.