Mold array process for semiconductor packages
US7691676B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2008 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Nov 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mold array process (MAP) for manufacturing a plurality of semiconductor packages is revealed. Firstly, a substrate strip including a plurality of substrate units arranged in an array within a molding area is provided. A plurality of chips are disposed on the substrate units. An encapsulant by molding is formed on the molding area of the substrate strip to continuously encapsulate the chips. During the molding process, an adjustable top mold is implemented where a cavity width between two opposing sidewalls inside a top mold chest can be adjusted to make the mold flow speeds at the center and at the side rails of the molding area the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.