Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
US7691752B2 · kind B2 · utility
42Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jul 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.