Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
US7692943B2 · kind B2 · utility
4Cited by
8References
6Claims
0Family size
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Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.