Patent · US Active

Low power scan test for integrated circuits

US7693676B1 · kind B1 · utility

13Cited by

5References

31Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Brion Keller · Binghamton, US
Vivek Chickermane · Ithaca, US
Sandeep Bhatia · Savanuru, IN

Key dates

Filing date	Feb 9, 2007
Grant date	Apr 6, 2010
Priority date	—
Expiry date	Jul 1, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318575
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Power dissipation during test is minimized by selecting particular values for the unused care-bits in values of the test vectors on a probabilistic basis to minimize switching, while preserving test vector quality.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.