Identification of ESD and latch-up weak points in an integrated circuit

US7694247B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Kai Esmark · Schwanau, DE
• Harald Gossner · Riemerling, DE
• Wolfgang Stadler · Hilpoltstein, DE
• Marin Streibl · Petershausen, DE

Key dates

• Filing date: Mar 17, 2005
• Grant date: Apr 6, 2010
• Expiry date: Apr 15, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/367
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.