Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer

US7700416B1 · kind B1 · utility

Assignee

• ACORN TECHNOLOGIES, INC. · US

Inventors

• Paul A. Clifton · Santa Monica, US
• Daniel J. Connelly · San Francisco, US
• R. Stockton Gaines · Santa Monica, US

Key dates

• Filing date: Apr 25, 2008
• Grant date: Apr 20, 2010
• Expiry date: Apr 25, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/938

Abstract

The process uses a sacrificial stressor layer to provide tensile strained surface regions for bulk silicon or silicon on insulator (SOI) substrates. The process deposits a sacrificial layer of silicon germanium on the surface of the substrate and then patterns the workpiece to form trenches extending through the silicon germanium stressor layer into the semiconductor substrate. The process fills the trenches with insulating materials and then removes the silicon germanium stressor layer, for example using wet etching, leaving a strained silicon or SOI substrate with a pattern of shallow trench isolation structures. The trench fill material is selected to stress the regions of silicon between the trenches to provide a tensile strained surface region to the semiconductor substrate. Such a strained semiconductor surface region can have improved mobility properties and so is advantageous for forming devices such as MOSFETs.