Bipolar and CMOS integration with reduced contact height

US7701015B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Zhong-Xiang He · South Burlington, US
• Bradley A. Orner · Saint Albans, US
• Vidhya Ramachandran · Cupertino, US
• Alvin J. Joseph · Williston, US
• Stephen A. St. Onge · Colchester, US
• Ping-Chuan Wang · Hopewell Junction, US

Key dates

• Filing date: Dec 16, 2003
• Grant date: Apr 20, 2010
• Expiry date: Oct 19, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.