Patent · US Active

Integrated circuit package system for chip on lead

US7701042B2 · kind B2 · utility

0Cited by

7References

20Claims

0Family size

Assignee

STATS ChipPAC, Ltd. · SG

Inventors

Shao Jian Chen · 安丰镇, CN
Wei Jin · Hangzhou City, CN
Bhoy Ching · Shanghai, CN
Taw Ming Lau · Shanghai, CN

Key dates

Filing date	Sep 18, 2007
Grant date	Apr 20, 2010
Priority date	—
Expiry date	Sep 18, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15787
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit package system includes providing an integrated circuit die having planar dimensions; forming a lead extended across one of the planar dimensions of the integrated circuit die; and applying an adhesive layer over the lead of a side opposite the integrated circuit die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.