Multi-step Cu seed layer formation for improving sidewall coverage
US7704886B2 · kind B2 · utility
12Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2008 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | May 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.