Circuit and method for parallel test of memory device
US7706199B2 · kind B2 · utility
5Cited by
5References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 10, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Mar 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.