Patent · US Active

Memory with level shifting word line driver and method thereof

US7706207B2 · kind B2 · utility

2Cited by

8References

13Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Thomas W. Liston · Austin, US
Shahnaz P. Chowdhury-Nagle · Austin, US
Perry H. Pelley · Austin, US

Key dates

Filing date	Sep 12, 2008
Grant date	Apr 27, 2010
Priority date	—
Expiry date	Sep 12, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.