Multi-ISA instruction fetch unit for a processor, and applications thereof
US7707389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30178
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction staging unit dispatches the expand instruction to a first recoder and the expandable instruction to a second recoder of a recoding unit. At least one information bit based on the expand instruction is generated at the first recoder. The second recoder uses the at least one information bit generated at the first recoder to recode the expandable instruction, and the recoded expandable instruction is placed in an instruction buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.