Patent · US Active

Instruction issue control within a multi-threaded in-order superscalar processor

US7707390B2 · kind B2 · utility

28Cited by

3References

37Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Emre Ozer · Godmanchester, GB
Vladimir Vasekin · Cambridge, GB
Stuart David Biles · Cambridge, GB

Key dates

Filing date	Apr 25, 2007
Grant date	Apr 27, 2010
Priority date	—
Expiry date	Jul 3, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/384
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.