CMOS level shifter circuit design
US7710183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2008 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356182
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.