Variable salicide block for resistance equalization in an array
US7713875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.