Mark Randolph
87Patents
20h-index
110Co-inventors
87Inventor score
Filing activity: Dec 16, 1997 → Oct 10, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6642573B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Emerging Cross-Sectional Technologies | 174 | Expired |
| US6275414A | Uniform bitline strapping of a non-volatile memory cell | Electricity | 111 | Expired |
| US7365389B1 | Memory cell having enhanced high-K dielectric | Electricity | 76 | Expired |
| US6639844B1 | Overerase correction method | Physics | 61 | Expired |
| US6639271B1 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Electricity | 57 | Expired |
| US5907781A | Process for fabricating an integrated circuit with a self-aligned contact | Electricity | 41 | Expired |
| US6768160B1 | Non-volatile memory cell and method of programming for improved data retention | Electricity | 41 | Expired |
| US6735114B1 | Method of improving dynamic reference tracking for flash memory unit | Physics | 37 | Expired |
| US6538270B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 37 | Expired |
| US6744675B1 | Program algorithm including soft erase for SONOS memory device | Physics | 36 | Expired |
| US6593606B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 35 | Expired |
| US7619932B2 | Algorithm for charge loss reduction and Vt distribution improvement | Physics | 34 | Active |
| US6967873B2 | Memory device and method using positive gate stress to recover overerased cell | Physics | 34 | Expired |
| US6834012B1 | Memory device and methods of using negative gate stress to correct over-erased memory cells | Physics | 34 | Expired |
| US7120063B1 | Flash memory cell and methods for programming and erasing | Electricity | 27 | Expired |
| US6693321B1 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Electricity | 24 | Expired |
| US7125763B1 | Silicided buried bitline process for a non-volatile memory cell | Electricity | 24 | Expired |
| US8938655B2 | Extending flash memory data retension via rewrite refresh | Physics | 21 | Active |
| US6795357B1 | Method for reading a non-volatile memory cell | Physics | 20 | Expired |
| US6934190B1 | Ramp source hot-hole programming for trap based non-volatile memory devices | Physics | 20 | Expired |
| US6770938B1 | Diode fabrication for ESD/EOS protection | Electricity | 18 | Expired |
| US6822909B1 | Method of controlling program threshold voltage distribution of a dual cell memory device | Physics | 16 | Expired |
| US6958272B2 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6477083B1 | Select transistor architecture for a virtual ground non-volatile memory cell array | Physics | 13 | Expired |
| US6465303B1 | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | Electricity | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.