CMOS transistor with a polysilicon gate electrode having varying grain size
US7714366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Feb 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.