Structure and fabrication method of flash memory
US7714374B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | May 11, 2010 |
| Priority date | — |
| Expiry date | Oct 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.