Patent · US Active

Carry-ripple adder

US7716270B2 · kind B2 · utility

3Cited by
8References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 13, 2006
Grant dateMay 11, 2010
Priority date
Expiry dateMar 11, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F7/503
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.