Patent · US Active

Method for manufacturing an integrated circuit including a transistor

US7718475B2 · kind B2 · utility

3Cited by

0References

24Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Matthias Goldbach · Dresden, DE
Erhard Landgraf · Dresden, DE
Michael Stadtmueller · Villach, AT
Moritz Haupt · Dresden, DE
Sven Schmidbauer · Dresden, DE
Tobias Mono · Dresden, DE
Jorg Radecker · Dresden, DE

Key dates

Filing date	Apr 13, 2007
Grant date	May 18, 2010
Priority date	—
Expiry date	Feb 21, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/664
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.