Techniques for enabling multiple Vt devices using high-K metal gate stacks

US7718496B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Martin M. Frank · Dobbs Ferry, US
• Arvind Kumar · Beaverton, US
• Vijay Narayanan · New York, US
• Vamsi K. Paruchuri · New York, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Oct 30, 2007
• Grant date: May 18, 2010
• Expiry date: Jun 3, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/125

Abstract

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.