Preservation circuit and methods to maintain values representing data in one or more layers of memory
US7719876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Dec 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.