Multi-level resistive memory cell using different crystallization speeds
US7719886B2 · kind B2 · utility
14Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2007 |
| Grant date | May 18, 2010 |
| Priority date | — |
| Expiry date | Feb 28, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.